Behavior of subthreshold conduction in junctionless transistors
DC Field | Value | Language |
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dc.contributor.author | Park, So Jeong | - |
dc.contributor.author | Jeon, Dae-Young | - |
dc.contributor.author | Montes, Laurent | - |
dc.contributor.author | Mouis, Mireille | - |
dc.contributor.author | Barraud, Sylvain | - |
dc.contributor.author | Kim, Gyu-Tae | - |
dc.contributor.author | Ghibaudo, Gerard | - |
dc.date.accessioned | 2021-09-03T19:43:55Z | - |
dc.date.available | 2021-09-03T19:43:55Z | - |
dc.date.created | 2021-06-16 | - |
dc.date.issued | 2016-10 | - |
dc.identifier.issn | 0038-1101 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/87433 | - |
dc.description.abstract | In this work, the effect of high channel doping concentration and unique structure of junctionless transistors (JLTs) is investigated in the subthreshold conduction regime. Both experimental results and simulation work show that JLTs have reduced portion of the diffusion conduction and lower effective barrier height between source/drain and the silicon channel in subthreshold regime, compared to conventional inversion-mode (IM) transistors. Finally, it leads to a relatively large DIBL value in JLTs, owing to degraded gate controllability on channel region and strong drain bias effect. However, JLTs showed a better immunity against short channel effect in terms of degradation of the effective barrier height value. (C) 2016 Elsevier Ltd. All rights reserved. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | PERGAMON-ELSEVIER SCIENCE LTD | - |
dc.subject | ELECTRICAL CHARACTERISTICS | - |
dc.subject | NANOWIRE TRANSISTORS | - |
dc.subject | VOLTAGE | - |
dc.subject | MOSFET | - |
dc.title | Behavior of subthreshold conduction in junctionless transistors | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Gyu-Tae | - |
dc.identifier.doi | 10.1016/j.sse.2016.06.007 | - |
dc.identifier.scopusid | 2-s2.0-84979695555 | - |
dc.identifier.wosid | 000382252000011 | - |
dc.identifier.bibliographicCitation | SOLID-STATE ELECTRONICS, v.124, pp.58 - 63 | - |
dc.relation.isPartOf | SOLID-STATE ELECTRONICS | - |
dc.citation.title | SOLID-STATE ELECTRONICS | - |
dc.citation.volume | 124 | - |
dc.citation.startPage | 58 | - |
dc.citation.endPage | 63 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.relation.journalWebOfScienceCategory | Physics, Condensed Matter | - |
dc.subject.keywordPlus | ELECTRICAL CHARACTERISTICS | - |
dc.subject.keywordPlus | NANOWIRE TRANSISTORS | - |
dc.subject.keywordPlus | VOLTAGE | - |
dc.subject.keywordPlus | MOSFET | - |
dc.subject.keywordAuthor | Junctionless transistors (JLT) | - |
dc.subject.keywordAuthor | Subthreshold conduction | - |
dc.subject.keywordAuthor | Less effective barrier height | - |
dc.subject.keywordAuthor | Subthreshold slope | - |
dc.subject.keywordAuthor | Diffusion current | - |
dc.subject.keywordAuthor | DIBL | - |
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