Detailed Information

Cited 0 time in webofscience Cited 0 time in scopus
Metadata Downloads

Unbiased Finite-Memory Digital Phase-Locked Loop

Full metadata record
DC Field Value Language
dc.contributor.authorYou, Sung Hyun-
dc.contributor.authorPak, Jung Min-
dc.contributor.authorAhn, Choon Ki-
dc.contributor.authorShi, Peng-
dc.contributor.authorLim, Myo Taeg-
dc.date.accessioned2021-09-03T21:36:26Z-
dc.date.available2021-09-03T21:36:26Z-
dc.date.created2021-06-18-
dc.date.issued2016-08-
dc.identifier.issn1549-7747-
dc.identifier.urihttps://scholar.korea.ac.kr/handle/2021.sw.korea/87994-
dc.description.abstractDigital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the unbiased finite-memory DPLL (UFMDPLL). The UFMDPLL is independent of noise covariance information, and it shows intrinsic robustness properties against incorrect noise information and quantization effects due to the finite-memory structure. Through numerical simulations, we show that the proposed DPLL is more robust against incorrect noise information and quantization effects than the conventional DPLLs are.-
dc.languageEnglish-
dc.language.isoen-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectFILTERS-
dc.subjectALGORITHM-
dc.subjectNOISE-
dc.subjectMODEL-
dc.subjectL(2)-
dc.subjectPLL-
dc.titleUnbiased Finite-Memory Digital Phase-Locked Loop-
dc.typeArticle-
dc.contributor.affiliatedAuthorAhn, Choon Ki-
dc.contributor.affiliatedAuthorLim, Myo Taeg-
dc.identifier.doi10.1109/TCSII.2016.2531138-
dc.identifier.scopusid2-s2.0-84984870587-
dc.identifier.wosid000381440000018-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.63, no.8, pp.798 - 802-
dc.relation.isPartOfIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS-
dc.citation.titleIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS-
dc.citation.volume63-
dc.citation.number8-
dc.citation.startPage798-
dc.citation.endPage802-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusFILTERS-
dc.subject.keywordPlusALGORITHM-
dc.subject.keywordPlusNOISE-
dc.subject.keywordPlusMODEL-
dc.subject.keywordPlusL(2)-
dc.subject.keywordPlusPLL-
dc.subject.keywordAuthorDigital phase-locked loop (DPLL)-
dc.subject.keywordAuthorfinite-memory structure-
dc.subject.keywordAuthorunbiasedness-
Files in This Item
There are no files associated with this item.
Appears in
Collections
College of Engineering > School of Electrical Engineering > 1. Journal Articles

qrcode

Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.

Related Researcher

Researcher Lim, Myo taeg photo

Lim, Myo taeg
공과대학 (전기전자공학부)
Read more

Altmetrics

Total Views & Downloads

BROWSE