Unbiased Finite-Memory Digital Phase-Locked Loop
DC Field | Value | Language |
---|---|---|
dc.contributor.author | You, Sung Hyun | - |
dc.contributor.author | Pak, Jung Min | - |
dc.contributor.author | Ahn, Choon Ki | - |
dc.contributor.author | Shi, Peng | - |
dc.contributor.author | Lim, Myo Taeg | - |
dc.date.accessioned | 2021-09-03T21:36:26Z | - |
dc.date.available | 2021-09-03T21:36:26Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2016-08 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/87994 | - |
dc.description.abstract | Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the unbiased finite-memory DPLL (UFMDPLL). The UFMDPLL is independent of noise covariance information, and it shows intrinsic robustness properties against incorrect noise information and quantization effects due to the finite-memory structure. Through numerical simulations, we show that the proposed DPLL is more robust against incorrect noise information and quantization effects than the conventional DPLLs are. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | FILTERS | - |
dc.subject | ALGORITHM | - |
dc.subject | NOISE | - |
dc.subject | MODEL | - |
dc.subject | L(2) | - |
dc.subject | PLL | - |
dc.title | Unbiased Finite-Memory Digital Phase-Locked Loop | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Ahn, Choon Ki | - |
dc.contributor.affiliatedAuthor | Lim, Myo Taeg | - |
dc.identifier.doi | 10.1109/TCSII.2016.2531138 | - |
dc.identifier.scopusid | 2-s2.0-84984870587 | - |
dc.identifier.wosid | 000381440000018 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.63, no.8, pp.798 - 802 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.volume | 63 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 798 | - |
dc.citation.endPage | 802 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | FILTERS | - |
dc.subject.keywordPlus | ALGORITHM | - |
dc.subject.keywordPlus | NOISE | - |
dc.subject.keywordPlus | MODEL | - |
dc.subject.keywordPlus | L(2) | - |
dc.subject.keywordPlus | PLL | - |
dc.subject.keywordAuthor | Digital phase-locked loop (DPLL) | - |
dc.subject.keywordAuthor | finite-memory structure | - |
dc.subject.keywordAuthor | unbiasedness | - |
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