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Unbiased Finite-Memory Digital Phase-Locked Loop

Authors
You, Sung HyunPak, Jung MinAhn, Choon KiShi, PengLim, Myo Taeg
Issue Date
8월-2016
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Digital phase-locked loop (DPLL); finite-memory structure; unbiasedness
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.63, no.8, pp.798 - 802
Indexed
SCIE
SCOPUS
Journal Title
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume
63
Number
8
Start Page
798
End Page
802
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/87994
DOI
10.1109/TCSII.2016.2531138
ISSN
1549-7747
Abstract
Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the unbiased finite-memory DPLL (UFMDPLL). The UFMDPLL is independent of noise covariance information, and it shows intrinsic robustness properties against incorrect noise information and quantization effects due to the finite-memory structure. Through numerical simulations, we show that the proposed DPLL is more robust against incorrect noise information and quantization effects than the conventional DPLLs are.
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