NOR logic function of a bendable combination of tunneling field-effect transistors with silicon nanowire channels
DC Field | Value | Language |
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dc.contributor.author | Kim, Yoonjoong | - |
dc.contributor.author | Jeon, Youngin | - |
dc.contributor.author | Kim, Minsuk | - |
dc.contributor.author | Kim, Sangsig | - |
dc.date.accessioned | 2021-09-04T03:32:06Z | - |
dc.date.available | 2021-09-04T03:32:06Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2016-02 | - |
dc.identifier.issn | 1998-0124 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/89687 | - |
dc.description.abstract | In this study, we propose a novel combination of tunneling field-effect transistors (TFETs) with asymmetrically doped p(+)-i-n(+) silicon nanowire (SiNW) channels on a bendable substrate. The combination of two n-channel SiNW-TFETs (NWTFETs) in parallel and two p-channel NWTFETs in series operates as a two-input NOR logic gate. The component NWTFETs with the n- and p-channels exhibit subthreshold swings (SSs) of 69 and 53 mV.dec(-1), respectively, and the on/off current ratios are similar to 10(6). The NOR logic operation is sustainable and reproducible for up to 1,000 bending cycles with a narrow transition width of similar to 0.26 V. The mechanical bendability of the bendable NWTFETs shows that they are stable and have good fatigue properties. To the best of our knowledge, this is the first study on the electrical and mechanical characteristics of a bendable NOR logic gate composed of NWTFETs. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | TSINGHUA UNIV PRESS | - |
dc.subject | SUBTHRESHOLD | - |
dc.title | NOR logic function of a bendable combination of tunneling field-effect transistors with silicon nanowire channels | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Sangsig | - |
dc.identifier.doi | 10.1007/s12274-015-0931-7 | - |
dc.identifier.scopusid | 2-s2.0-84958121338 | - |
dc.identifier.wosid | 000371798800022 | - |
dc.identifier.bibliographicCitation | NANO RESEARCH, v.9, no.2, pp.499 - 506 | - |
dc.relation.isPartOf | NANO RESEARCH | - |
dc.citation.title | NANO RESEARCH | - |
dc.citation.volume | 9 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 499 | - |
dc.citation.endPage | 506 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Chemistry | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Chemistry, Physical | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | SUBTHRESHOLD | - |
dc.subject.keywordAuthor | silicon nanowire array | - |
dc.subject.keywordAuthor | field-effect transistor | - |
dc.subject.keywordAuthor | tunneling | - |
dc.subject.keywordAuthor | NOR logic gate | - |
dc.subject.keywordAuthor | bendable substrate | - |
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