Theoretical and Experimental Investigation of Graphene/High-kappa/p-Si Junctions
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shim, Jaewoo | - |
dc.contributor.author | Yoo, Gwangwe | - |
dc.contributor.author | Kang, Dong-Ho | - |
dc.contributor.author | Jung, Woo-Shik | - |
dc.contributor.author | Byun, Young-Chul | - |
dc.contributor.author | Kim, Hyoungsub | - |
dc.contributor.author | Kang, Won Tae | - |
dc.contributor.author | Yu, Woo Jong | - |
dc.contributor.author | Yu, Hyun-Yong | - |
dc.contributor.author | Park, Yongkook | - |
dc.contributor.author | Park, Jin-Hong | - |
dc.date.accessioned | 2021-09-04T04:26:51Z | - |
dc.date.available | 2021-09-04T04:26:51Z | - |
dc.date.created | 2021-06-18 | - |
dc.date.issued | 2016-01 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/89922 | - |
dc.description.abstract | Here, we theoretically and experimentally investigate the impact of a high-kappa layer inserted between graphene and p-Si in a graphene/Si junction. We have achieved 86-fold and 222-fold reductions in a specific contact resistivity (rho(c)) by inserting 1-nm-thick Al2O3 and 2-nm-thick TiO2 in the graphene-semiconductor junction, respectively, corresponding to lowering the effective barrier height by 0.24 and 0.12 eV. Furthermore, we propose a graphene-induced gap state model that simultaneously considers the graphene's modulation by a gate bias and the effect of the high-kappa insertion. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | GATE | - |
dc.title | Theoretical and Experimental Investigation of Graphene/High-kappa/p-Si Junctions | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Yu, Hyun-Yong | - |
dc.identifier.doi | 10.1109/LED.2015.2497714 | - |
dc.identifier.scopusid | 2-s2.0-84961626011 | - |
dc.identifier.wosid | 000367270700001 | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.37, no.1, pp.4 - 7 | - |
dc.relation.isPartOf | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 37 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 4 | - |
dc.citation.endPage | 7 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | GATE | - |
dc.subject.keywordAuthor | Graphene | - |
dc.subject.keywordAuthor | high-kappa | - |
dc.subject.keywordAuthor | Schottky | - |
dc.subject.keywordAuthor | GS junction | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
(02841) 서울특별시 성북구 안암로 14502-3290-1114
COPYRIGHT © 2021 Korea University. All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.