Memory Interfaces: Past, Present, and Future
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, C. | - |
dc.contributor.author | Lee, H.-W. | - |
dc.contributor.author | Song, J. | - |
dc.date.accessioned | 2021-09-04T08:48:03Z | - |
dc.date.available | 2021-09-04T08:48:03Z | - |
dc.date.created | 2021-06-17 | - |
dc.date.issued | 2016 | - |
dc.identifier.issn | 1943-0582 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/91360 | - |
dc.description.abstract | Over the last few decades, the bandwidth of dynamic random-access memory (DRAM) has increased significantly through innovative architectures and circuit-level techniques to overcome the well-known memory wall problem. We can understand the past challenges of DRAM input/output (I/O) by investigating the technologies utilized for DRAM I/O in the transition from single-data-rate (SDR) synchronous DRAM (SDRAM)to double-data-rate (DDR) SDRAM. Recently developed versions of low-power DDR four (LPDDR4) and synchronous graphics DDR five (GDDR5) employ new I/O features for further bandwidth increase. Looking beyond LPDDR4 and GDDR5, what should be done to make another jump in bandwidth increase for DRAM? © 2016 IEEE. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.subject | Bandwidth | - |
dc.subject | Random access storage | - |
dc.subject | Circuit levels | - |
dc.subject | Data rates | - |
dc.subject | Double data rate | - |
dc.subject | Dynamic random access memory | - |
dc.subject | Input/output | - |
dc.subject | Memory interface | - |
dc.subject | Memory wall | - |
dc.subject | Synchronous drams | - |
dc.subject | Dynamic random access storage | - |
dc.title | Memory Interfaces: Past, Present, and Future | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, C. | - |
dc.identifier.doi | 10.1109/MSSC.2016.2546659 | - |
dc.identifier.scopusid | 2-s2.0-84976631779 | - |
dc.identifier.bibliographicCitation | IEEE Solid-State Circuits Magazine, v.8, no.2, pp.23 - 34 | - |
dc.relation.isPartOf | IEEE Solid-State Circuits Magazine | - |
dc.citation.title | IEEE Solid-State Circuits Magazine | - |
dc.citation.volume | 8 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 23 | - |
dc.citation.endPage | 34 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Bandwidth | - |
dc.subject.keywordPlus | Random access storage | - |
dc.subject.keywordPlus | Circuit levels | - |
dc.subject.keywordPlus | Data rates | - |
dc.subject.keywordPlus | Double data rate | - |
dc.subject.keywordPlus | Dynamic random access memory | - |
dc.subject.keywordPlus | Input/output | - |
dc.subject.keywordPlus | Memory interface | - |
dc.subject.keywordPlus | Memory wall | - |
dc.subject.keywordPlus | Synchronous drams | - |
dc.subject.keywordPlus | Dynamic random access storage | - |
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