Memory Interfaces: Past, Present, and Future
- Authors
- Kim, C.; Lee, H.-W.; Song, J.
- Issue Date
- 2016
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Citation
- IEEE Solid-State Circuits Magazine, v.8, no.2, pp.23 - 34
- Indexed
- SCOPUS
- Journal Title
- IEEE Solid-State Circuits Magazine
- Volume
- 8
- Number
- 2
- Start Page
- 23
- End Page
- 34
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/91360
- DOI
- 10.1109/MSSC.2016.2546659
- ISSN
- 1943-0582
- Abstract
- Over the last few decades, the bandwidth of dynamic random-access memory (DRAM) has increased significantly through innovative architectures and circuit-level techniques to overcome the well-known memory wall problem. We can understand the past challenges of DRAM input/output (I/O) by investigating the technologies utilized for DRAM I/O in the transition from single-data-rate (SDR) synchronous DRAM (SDRAM)to double-data-rate (DDR) SDRAM. Recently developed versions of low-power DDR four (LPDDR4) and synchronous graphics DDR five (GDDR5) employ new I/O features for further bandwidth increase. Looking beyond LPDDR4 and GDDR5, what should be done to make another jump in bandwidth increase for DRAM? © 2016 IEEE.
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