Rail-to-rail regulating voltage-controlled oscillator with low supply and ground noise sensitivity
- Authors
- Ko, Jaehong; An, Chang-Ho; Kwon, Chan-Keun; Kim, Soo-Won; Kim, Chulwoo
- Issue Date
- 19-11월-2015
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Keywords
- voltage-controlled oscillators; sensitivity analysis; low-power electronics; clock and data recovery circuits; driver circuits; CMOS integrated circuits; digital-analogue conversion; phase locked loops; rail-to-rail regulating voltage-controlled oscillator; ground noise sensitivity; R-to-R regulating VCO; multiple-phase clock; clock and data recovery; display driver IC; DDI; 1P6M CMOS technology; interface block; DAC; phase- locked loop; flat-panel display interface; complementary metal oxide semiconductor; digital-analog converter; size 0; 18 mum; voltage 1; 8 V; size 1; 6 mum; voltage 18 V; frequency 140 MHz to 240 MHz; voltage 0; 5 V to 1; 2 V
- Citation
- ELECTRONICS LETTERS, v.51, no.24, pp.1980 - 1981
- Indexed
- SCIE
SCOPUS
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 51
- Number
- 24
- Start Page
- 1980
- End Page
- 1981
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/91881
- DOI
- 10.1049/el.2015.3128
- ISSN
- 0013-5194
- Abstract
- A rail-to-rail (R-to-R) regulating voltage-controlled oscillator (VCO) is employed to generate multiple-phase clocks for clock and data recovery in a display driver IC (DDI). To achieve a low supply and ground noise sensitivity, the proposed R-to-R regulating method generates VSP and VSN as the supply and the ground of the VCO instead of VDD and VSS. By applying the proposed method, the frequency-VDD variation rate of the VCO (%-f(VCO)/%-VDD) changes from 3.5%-f(VCO)/1%-VDD to 0.0073%-f(VCO)/1%-VDD within the V-ctrl range of 0.5-1.2 V. The DDI is fabricated in a 1P6M 0.18 m 1.8 V CMOS technology for the interface block and in a 1.6 m 18 V CMOS technology for the DAC. The R-to-R regulating VCO has a tuning range of 140-240 MHz with linear and small gain (K-VCO) characteristics, and is suitable for the phase-locked loop used in flat-panel display interfaces that operate from 0.3 to 2 Gbits/s.
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