A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS
DC Field | Value | Language |
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dc.contributor.author | Chung, Hayun | - |
dc.contributor.author | Deniz, Zeynep Toprak | - |
dc.contributor.author | Rylyakov, Alexander | - |
dc.contributor.author | Bulzacchelli, John | - |
dc.contributor.author | Friedman, Daniel | - |
dc.contributor.author | Wei, Gu-Yeon | - |
dc.date.accessioned | 2021-09-04T11:12:26Z | - |
dc.date.available | 2021-09-04T11:12:26Z | - |
dc.date.created | 2021-06-10 | - |
dc.date.issued | 2015-11 | - |
dc.identifier.issn | 0925-1030 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/92118 | - |
dc.description.abstract | This paper presents a 7.5 GS/s, 4.5 bit flash analog-to-digital converter (ADC) for high-speed backplane communication. A two-stage track-and-hold (T/H) structure enables high input bandwidth and low power consumption at the same time. A sampling clock duty cycle control technique, which allocates more tracking time to the bandwidth-limited second T/H stage, facilitates high sampling rates. A digital offset correction scheme compensates both random and systematic offsets due to process variation and T/H amplifier gain nonlinearity, simultaneously. Two test-chip prototypes were fabricated in a 65 nm CMOS process. Experimental results of a standalone ADC chip demonstrate 3.8 effective number of bits (ENOB) at 7.5 GS/s. The figure-of-merit (FOM) of the standalone ADC is 0.49 pJ/conversion-step. The second test chip combines two ADCs together in order to demonstrate a time-interleaved ADC (TI-ADC) for use in high-speed backplane receivers. The TI-ADC operates at 10.24 GS/s while achieving 3.5 ENOB and 0.65 pJ/conversion-step FOM. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | SPRINGER | - |
dc.title | A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Chung, Hayun | - |
dc.identifier.doi | 10.1007/s10470-015-0624-x | - |
dc.identifier.scopusid | 2-s2.0-84942985486 | - |
dc.identifier.wosid | 000361984600008 | - |
dc.identifier.bibliographicCitation | ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, v.85, no.2, pp.299 - 310 | - |
dc.relation.isPartOf | ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | - |
dc.citation.title | ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | - |
dc.citation.volume | 85 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 299 | - |
dc.citation.endPage | 310 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | High-speed | - |
dc.subject.keywordAuthor | Analog-to-digital converter | - |
dc.subject.keywordAuthor | Two-stage track-and-hold amplifier | - |
dc.subject.keywordAuthor | Duty-cycle control | - |
dc.subject.keywordAuthor | Backplane receiver | - |
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