A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS
- Authors
- Chung, Hayun; Deniz, Zeynep Toprak; Rylyakov, Alexander; Bulzacchelli, John; Friedman, Daniel; Wei, Gu-Yeon
- Issue Date
- 11월-2015
- Publisher
- SPRINGER
- Keywords
- High-speed; Analog-to-digital converter; Two-stage track-and-hold amplifier; Duty-cycle control; Backplane receiver
- Citation
- ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, v.85, no.2, pp.299 - 310
- Indexed
- SCIE
SCOPUS
- Journal Title
- ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
- Volume
- 85
- Number
- 2
- Start Page
- 299
- End Page
- 310
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/92118
- DOI
- 10.1007/s10470-015-0624-x
- ISSN
- 0925-1030
- Abstract
- This paper presents a 7.5 GS/s, 4.5 bit flash analog-to-digital converter (ADC) for high-speed backplane communication. A two-stage track-and-hold (T/H) structure enables high input bandwidth and low power consumption at the same time. A sampling clock duty cycle control technique, which allocates more tracking time to the bandwidth-limited second T/H stage, facilitates high sampling rates. A digital offset correction scheme compensates both random and systematic offsets due to process variation and T/H amplifier gain nonlinearity, simultaneously. Two test-chip prototypes were fabricated in a 65 nm CMOS process. Experimental results of a standalone ADC chip demonstrate 3.8 effective number of bits (ENOB) at 7.5 GS/s. The figure-of-merit (FOM) of the standalone ADC is 0.49 pJ/conversion-step. The second test chip combines two ADCs together in order to demonstrate a time-interleaved ADC (TI-ADC) for use in high-speed backplane receivers. The TI-ADC operates at 10.24 GS/s while achieving 3.5 ENOB and 0.65 pJ/conversion-step FOM.
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Collections - College of Science and Technology > Department of Electronics and Information Engineering > 1. Journal Articles
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