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Explicit Analytical Current-Voltage Model for Double-Gate Junctionless Transistors

Authors
Hwang, Byeong-WoonYang, Ji-WoonLee, Seok-Hee
Issue Date
1월-2015
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Compact modeling; junctionless (JL) transistor; multigate MOSFET; variability
Citation
IEEE TRANSACTIONS ON ELECTRON DEVICES, v.62, no.1, pp.171 - 177
Indexed
SCIE
SCOPUS
Journal Title
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume
62
Number
1
Start Page
171
End Page
177
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/94748
DOI
10.1109/TED.2014.2371075
ISSN
0018-9383
Abstract
An explicit analytical model for long-channel double-gate junctionless transistors is presented in each operation mode: 1) full depletion; 2) partial depletion; and 3) accumulation. The proposed model calculates potentials, electric fields, mobile charges, and drain current without any implicit function or special functions. The results obtained with the proposed model agree well with the results obtained with a 2-D technology computer-aided design simulation in all modes of operation and for various device structures. Furthermore, a physical insight is provided into reducing variability using the threshold voltage model.
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