반도체 공정에서의 Wafer Map Image 분석 방법론Wafer Map Image Analysis Methods in Semiconductor Manufacturing System
- Other Titles
- Wafer Map Image Analysis Methods in Semiconductor Manufacturing System
- Authors
- 유영지; 안대웅; 박승환; 백준걸
- Issue Date
- 2015
- Publisher
- 대한산업공학회
- Keywords
- Semiconductor; Wafer test; Package test; Wafer map image; Fail bit pattern
- Citation
- 대한산업공학회지, v.41, no.3, pp.267 - 274
- Indexed
- KCI
- Journal Title
- 대한산업공학회지
- Volume
- 41
- Number
- 3
- Start Page
- 267
- End Page
- 274
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/95554
- DOI
- 10.7232/JKIIE.2015.41.3.267
- ISSN
- 1225-0988
- Abstract
- In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.
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Collections - College of Engineering > School of Industrial and Management Engineering > 1. Journal Articles
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