2.56 GHz sub-harmonically injection-locked PLL with cascaded DLL for multi-phase injection
- Authors
- Choi, Changsung; Hwang, Sewook; Song, Junyoung; Kim, Chulwoo
- Issue Date
- 20-Nov-2014
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Citation
- ELECTRONICS LETTERS, v.50, no.24, pp.1803 - U165
- Indexed
- SCIE
SCOPUS
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 50
- Number
- 24
- Start Page
- 1803
- End Page
- U165
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/96748
- DOI
- 10.1049/el.2014.3191
- ISSN
- 0013-5194
- Abstract
- A 2.56 GHz injection-locked phase-locked loop (ILPLL) cascaded with a delay-locked loop (DLL) for minimising phase noise is presented. Generally, an ILPLL includes an injection-locked voltage-controlled oscillator (ILVCO), which is directly injected with the reference clock phase. However, the proposed scheme connects the output multi-phased clocks of the DLL to the injection node and they can be selected with turn on/off switches. This can shorten the realignment time of the VCO phases and thus the in-band phase noise is decreased. The proposed circuit is implemented in a 65 nm CMOS technology, and reduces the phase noise by 10.86 dBc/Hz at a 1 MHz offset with 16 multi-phased injections, compared with a conventional PLL.
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