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Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces
- Authors
- Lee, Hyun-Woo; Kim, Chulwoo
- Issue Date
- Apr-2014
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Analog delay-locked loop (DLL); DDR1; DDR2; DDR3; DLL; digital DLL; duty cycle corrector (DCC); dynamic random access memory (DRAM); GDDR3; half-clock phase control; half-clock phase inverting; harmonic lock; lock range; power down exit time; register-controlled DLL; tDQSCK; variable delay line; wake-up time
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.22, no.4, pp.701 - 711
- Indexed
- SCIE
SCOPUS
- Volume
- 22
- Number
- 4
- Start Page
- 701
- End Page
- 711
- ISSN
- 1063-8210
- Abstract
- In this paper, delay-locked loops (DLLs) used in dynamic random access memory (DRAM) are analyzed. DLLs can be categorized into digital-or analog-based topologies. This analysis starts with an explanation of technology trends regarding DLL for DRAM in the early 1990s and describes important DLL specifications and design approaches necessary for DLL use in DRAM: lock time, lock range, lock cycles, tDQSCK (DQS rising edge output access time from the rising edge of CK), and wake-up time from power down modes. DLLs have been widely used since 2000 to satisfy high operating speed requirements inherent in DRAMs. Finally, referring to studies published from 2000 to 2011, trends regarding power consumption, jitter, relationship between power and jitter, lock range, lock cycles, and wake-up time from power down are analyzed.
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