VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Jangwon | - |
dc.contributor.author | Park, Jongsun | - |
dc.contributor.author | Bhunia, Swarup | - |
dc.date.accessioned | 2021-09-05T11:35:28Z | - |
dc.date.available | 2021-09-05T11:35:28Z | - |
dc.date.created | 2021-06-15 | - |
dc.date.issued | 2014-02 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/99354 | - |
dc.description.abstract | Increasing process variations coupled with aggressive scaling of cell area and operating voltage in the quest of higher density and lower power have greatly affected the reliability of on-chip memory. Error correction code (ECC) has been traditionally used inside memory to provide uniform protection to all bits in a code word. They suffer from either adequate protection against multibit failures or large overhead due to encoding/decoding logic and parity bits. To address this issue, we present a variable data-length ECC (VL-ECC) for the embedded memory devices of digital signal processors, in which the data length of ECC can be dynamically reconfigured to preferentially protect the relatively more important bits. In the proposed VL-ECC, when the number of failures exceeds the error correction capability, the data length of ECC is reduced to focus on the relatively more important higher order data bit parts, thereby minimizing system quality degradation due to bit failures. When the proposed VL-ECC is applied to the embedded memory devices of an H. 264 processor, average peak signal-to-noise-ratio improvements of up to 5.12 dB are achieved compared with the conventional ECC under supply voltage of 800 mV or lower. With the fast Fourier transform processor, signal-to-quantization noise ratio is improved by up to 5.2 dB. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | ARCHITECTURE | - |
dc.title | VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Jongsun | - |
dc.identifier.doi | 10.1109/TCSII.2013.2291091 | - |
dc.identifier.scopusid | 2-s2.0-84895922225 | - |
dc.identifier.wosid | 000332110500012 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.61, no.2, pp.120 - 124 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.volume | 61 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 120 | - |
dc.citation.endPage | 124 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
dc.subject.keywordAuthor | Embedded static random access memory (SRAM) | - |
dc.subject.keywordAuthor | error correction code (ECC) | - |
dc.subject.keywordAuthor | fast Fourier transform (FFT) | - |
dc.subject.keywordAuthor | H.264 | - |
dc.subject.keywordAuthor | low voltage operation | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
(02841) 서울특별시 성북구 안암로 14502-3290-1114
COPYRIGHT © 2021 Korea University. All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.