Layered Trench Gate Exhibiting Source/Drain Over-Etch Immunity Without Punch-Through Stopper

초록

This work proposes a Layered Trench Gate (LTG) architecture to suppress leakage current as well as enhance process variation immunity in gate-all-around field-effect transistors (GAAFETs) without requiring punch-through stopper (PTS) doping. By eliminating PTS doping, the LTG avoids drawbacks such as increased band-to-band tunneling and random dopant fluctuations while maintaining strong gate-to-channel electrostatics through a layered trench design. We benchmark the LTG against conventional leakage control methods-PTS, bottom dielectric isolation (BDI), local BDI (LBDI), and trench gate (TG)-under realistic fabrication variations, particularly a 6 nm source/drain over-etch. Under these conditions, the PTS structure suffers a 2,840-fold increase in off-current and a 3.84 & times;10(-3)-fold reduction in on/off ratio, whereas the LTG shows only 21.5-fold and 4.69 & times;10(-2)-fold changes, respectively, demonstrating significantly improved robustness. A 3-stage ring oscillator simulation reveals that the LTG achieves 1.9% shorter delay and 2.4% lower dynamic power under identical conditions. These results highlight the LTG's enhanced gate-to-channel control and minimized parasitic capacitance, establishing it as a strong candidate for future nanoscale devices demanding superior variation immunity and power-performance efficiency.

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