Analysis of Ring Oscillator Characteristics Induced by Line Edge Roughness Using Convolution Neural Network

초록

The gate-all-around field-effect transistors (GAAFETs) are highly susceptible to performance variations caused by process-induced random variation. Line edge roughness (LER) is a dominant source that broadens the threshold voltage (V-th) distribution and causes stage-specific differences in the ring oscillator (RO) performance. Although LER is a process variation, systematic variations further amplify its impact. To accurately assess the delay time and dynamic power under various LER conditions, a comprehensive framework combining TCAD simulations, HSPICE, and machine learning (ML) was proposed. LER surfaces were generated using an autocovariance function (ACVF), and the nanosheet transistor characteristics were modeled using Sentaurus TCAD to evaluate the electrical properties. The variations in delay and power were further analyzed through HSPICE simulations. A convolutional neural network (CNN) was trained on X-cut and Y-cut cross-sectional images of devices under different LER conditions to predict these performance metrics. The proposed model achieved a mean squared error (mse) of 0.000205 or lower, demonstrating high accuracy. The results showed that LER significantly affected the device characteristics, with stage-specific variation in the RO impacting both delay and power. When uniform LER was applied across all stages, simultaneous switching noise (SSN) amplified the power variability, while the delay variability was primarily influenced by fluctuations in the transistor's electrical properties. While simulations considering LER-induced circuit performance were time-consuming, the CNN-based ML model proved to be highly effective in accurately predicting device and circuit performance.

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