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Digital calibration technique using a signed counter for charge pump mismatch in phase-locked loops
- Issue Date
- 11월-2013
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Keywords
- calibration; CMOS digital integrated circuits; digital phase locked loops; charge pump circuits; digital calibration technique; signed counter; charge pump mismatch; phase-locked loops; standard CMOS technology; size 0; 18 mum; time 32; 8 mus; power 6; 2 mW; voltage 1; 8 V
- Citation
- IET CIRCUITS DEVICES & SYSTEMS, v.7, no.6, pp.313 - 318
- Indexed
- SCIE
SCOPUS
- Journal Title
- IET CIRCUITS DEVICES & SYSTEMS
- Volume
- 7
- Number
- 6
- Start Page
- 313
- End Page
- 318
- ISSN
- 1751-858X
- Abstract
- The authors adopt a digital technique to calibrate the current mismatch of the charge pump in phase-locked loops. The proposed digital calibration technique using a signed counter reduces the calibration time up to a minimum of 64% as compared with the other techniques. This technique is designed by a standard 0.18 m CMOS technology. The calibration time is 32.8 s, the average power is 6.2 mW at a 1.8 V power supply and the effective area is 0.263 mm(2).
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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