Current adjustable clock distribution network scheme for GDDR5

Abstract

Presented is a current adjustable clock distribution network for GDDR5. In general, GDDR5 uses a current mode logic (CML) buffer as the global driver of the clock distribution. The wide-frequency range conventional CML buffer is designed to the fastest frequency. However, the CML buffer consumes constant current at all frequencies. For this reason, the conventional buffer dissipates current more than necessary at low frequencies. A proposed current adjustable clock distribution network scheme adjusts the amount of the current consumption of the global driver according to the clock frequency. The proposed scheme is implemented in 65 nm CMOS technology, reduces power consumption by 17.7% in the wide frequency range from an average 10.26 mW of the conventional scheme to 8.44 mW.