A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection
- Authors
- Song, Junyoung; Jung, Inhwa; Song, Minyoung; Kwak, Young-Ho; Hwang, Sewook; Kim, Chulwoo
- Issue Date
- Feb-2013
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Clock and data recovery; phase and frequency detection; phase detection; referenceless transceiver
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.60, no.2, pp.268 - 278
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
- Volume
- 60
- Number
- 2
- Start Page
- 268
- End Page
- 278
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/104029
- DOI
- 10.1109/TCSI.2012.2215779
- ISSN
- 1549-8328
- Abstract
- This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architecture for DisplayPort v1.1a. The jitter of the generated clock at the Tx PLL is 3.28 ps(rms) at 2.7 Gb/s with 1.2 V supply. The eye opening of the transmitter output with 3 m cable is 0.54 UI. The measured jitter of the recovered clock at the CDR is 1.57 ps(rms), and BER is less than 10(-12). The receiver consumes 23 mW at 2.7 Gb/s with 1.2 V supply. The CDR core and transceiver occupy 0.07 mm(2) and 0.94 mm(2), respectively, in a 0.13 mu m 1P8M CMOS process.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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