Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip
- Authors
- Phi-Hung Pham; Park, Jongsun; Phuong Mau; Kim, Chulwoo
- Issue Date
- 2월-2012
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Backtracking; circuit-switched; dynamic path-setup; guaranteed throughput; network-on-chip (NoC); on-chip switch; source synchronous; wave-pipeline
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.2, pp.270 - 283
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 20
- Number
- 2
- Start Page
- 270
- End Page
- 283
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/106140
- DOI
- 10.1109/TVLSI.2010.2096520
- ISSN
- 1063-8210
- Abstract
- It is a challenging task in a network-on-chip to design an on-chip switch/router to dynamically support (hard) guaranteed throughput under very tight on-chip constraints of power, timing, area, and time-to-market. This paper presents the design and implementation of a novel pipeline circuit-switched switch to support guaranteed throughput. The proposed circuit-switched switch, based on a backtracking probing path setup, operates with a source-synchronous wave-pipeline approach. The switch can support a dead- and live-lock free dynamic path-setup scheme and can achieve high bandwidth and high area and energy efficiency. A silicon-proven prototype of a 16-bit-data 5-bidirectional-port switch in a four-metal-layer 0.18-mu m CMOS standard-cell technology can yield an aggregate data bandwidth of up to 73.84 Gb/s, while occupying only a modest area of 0.0315 mm(2). The synthe-sizable implementation of the proposed switch also results in a cost-effective design, fast development time, and portability.
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