New Bit Parallel Multiplier With Low Space Complexity for All Irreducible Trinomials Over GF(2(n))
- Authors
- Cho, Young In; Chang, Nam Su; Kim, Chang Han; Park, Young-Ho; Hong, Seokhie
- Issue Date
- 10월-2012
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Bit-parallel multiplier; finite field; irreducible trinomial; Mastrovito multiplication; polynomial basis
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.10, pp.1903 - 1908
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 20
- Number
- 10
- Start Page
- 1903
- End Page
- 1908
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/107346
- DOI
- 10.1109/TVLSI.2011.2162594
- ISSN
- 1063-8210
- Abstract
- Koc and Sunar proposed an architecture of the Mastrovito multiplier for the irreducible trinomial f(x) = x(n) + x(k) + 1, where k not equal n/2 to reduce the time complexity. Also, many multipliers based on the Karatsuba-Ofman algorithm (KOA) was proposed that sacrificed time efficiency for low space complexity. In this paper, a new multiplication formula which is a variant of KOA presented. We also provide a straightforward architecture of a non-pipelined bit-parallel multiplier using the new formula. The proposed multiplier has lower space complexity than and comparable time complexity to previous Mastrovito multipliers' for all irreducible trinomials.
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