Design of an OpenVG Hardware Rendering Engine
- Authors
- Shen, Yong-Luo; Kim, Seok-Jae; Seo, Sang-Woo; Lee, Hyun-Goo; Oh, Hyeong-Cheol
- Issue Date
- 12월-2011
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- OpenVG; 2D vector graphics; hardware rendering engine
- Citation
- IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E94D, no.12, pp.2409 - 2417
- Journal Title
- IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
- Volume
- E94D
- Number
- 12
- Start Page
- 2409
- End Page
- 2417
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/110967
- DOI
- 10.1587/transinf.E94.D.2409
- ISSN
- 1745-1361
- Abstract
- This paper introduces a hardware engine for rendering two-dimensional vector graphics based on the OpenVG standard in portable devices. We focus on two design challenges posed by the rendering engines: the number of vertices to represent the images and the amount of memory usage. Redundant vertices are eliminated using adaptive tessellation, in which the redundancy can be judged using a proposed cost-per-quality measure. A simplified edge-flag rendering algorithm and the scanline-based rendering scheme are adopted to reduce external memory access. The designed rendering engine occupies approximately 173K gates and can satisfy real-time requirements of many applications when it is implemented using a 0.18 mu m, 1.8 V CMOS standard cell library. An FPGA prototype using a system-on-a-chip platform has been developed and tested.
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Collections - College of Science and Technology > Department of Electronics and Information Engineering > 1. Journal Articles
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