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A 140 Mb/s to 1.96 Gb/s Referenceless Transceiver With 7.2 mu s Frequency Acquisition Time
- Authors
- Jung, Inhwa; Shin, Daejung; Kim, Taejin; Kim, Chulwoo
- Issue Date
- 7월-2011
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Clock and data recovery (CDR); embedded clock; linear PD; low-jitter; low voltage differential signaling (LVDS); transceiver; wide-range
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.19, no.7, pp.1310 - 1315
- Indexed
- SCIE
SCOPUS
- Volume
- 19
- Number
- 7
- Start Page
- 1310
- End Page
- 1315
- ISSN
- 1063-8210
- Abstract
- This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 mu s. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The rms jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm(2) in a 0.25-mu m 1P5M CMOS technology.
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