Detailed Information
Cited 0 time in 
Cited 0 time in 
Cited 0 time in
Metadata Downloads
Charge-redistribution DAC with double bit processing in single capacitor
- Authors
- Yang, S. H.; Lee, K. S.; Kim, S.; Lee, Y. M.
- Issue Date
- 3-3월-2011
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Citation
- ELECTRONICS LETTERS, v.47, no.5, pp.312 - U36
- Indexed
- SCIE
SCOPUS
- Journal Title
- ELECTRONICS LETTERS
- Volume
- 47
- Number
- 5
- Start Page
- 312
- End Page
- U36
- ISSN
- 0013-5194
- Abstract
- An 8-bit charge-redistribution DAC with double bit processing in a single capacitor is proposed. The proposed DAC requires only four binary weighted capacitors where each capacitor converts 2-bit digital data into an analogue value in a single conversion step. Therefore, capacitor area can be effectively reduced without affecting the conversion time. The proposed 8-bit DAC is fabricated using CMOS 0.18 mu m technology with a core area of 0.0934 mm(2).
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.