Spatial Distribution of Interface Traps in Sub-50-nm Recess-Channel-Type DRAM Cell Transistors
DC Field | Value | Language |
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dc.contributor.author | Chung, Eun-Ae | - |
dc.contributor.author | Kim, Young-Pil | - |
dc.contributor.author | Park, Min-Chul | - |
dc.contributor.author | Nam, Kab-Jin | - |
dc.contributor.author | Lee, Sung-Sam | - |
dc.contributor.author | Min, Ji-Young | - |
dc.contributor.author | Yang, Giyoung | - |
dc.contributor.author | Shin, Yu-Gyun | - |
dc.contributor.author | Choi, Siyoung | - |
dc.contributor.author | Jin, Gyoyoung | - |
dc.contributor.author | Moon, Joo-Tae | - |
dc.contributor.author | Kim, Sangsig | - |
dc.date.accessioned | 2021-09-07T16:30:33Z | - |
dc.date.available | 2021-09-07T16:30:33Z | - |
dc.date.created | 2021-06-14 | - |
dc.date.issued | 2011-01 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/113356 | - |
dc.description.abstract | The spatial distribution of the interface traps in dynamic random access memory (DRAM) cell transistors having deeply recessed channels for sub-50-nm technology was evaluated by the charge pumping method and 3-D device simulations for the first time. The lateral distribution of the interface traps can be profiled before and after applying Fowler-Nordheim (F-N) gate stress. The experimental results show that the distribution of the interface traps is significantly correlated with the source/drain doping concentration, and this 3-D DRAM cell transistor was found to have greater immunity to F-N gate stress in the gate-drain overlapping region than in the channel region, due to the gate oxide thickness profile of the recess-channel-type structure. This lateral profiling of the interface traps in DRAM cell transistors should be very useful for refresh modeling and future DRAM device designs intended to improve the performance. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | CHARGE-PUMPING MEASUREMENTS | - |
dc.subject | DENSITY | - |
dc.subject | LEAKAGE | - |
dc.title | Spatial Distribution of Interface Traps in Sub-50-nm Recess-Channel-Type DRAM Cell Transistors | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Sangsig | - |
dc.identifier.doi | 10.1109/LED.2010.2085416 | - |
dc.identifier.wosid | 000285844400027 | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.32, no.1, pp.81 - 83 | - |
dc.relation.isPartOf | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 32 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 81 | - |
dc.citation.endPage | 83 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | CHARGE-PUMPING MEASUREMENTS | - |
dc.subject.keywordPlus | DENSITY | - |
dc.subject.keywordPlus | LEAKAGE | - |
dc.subject.keywordAuthor | Cell transistor | - |
dc.subject.keywordAuthor | charge pumping (CP) | - |
dc.subject.keywordAuthor | interface traps | - |
dc.subject.keywordAuthor | MOSFET | - |
dc.subject.keywordAuthor | recessed-channel array transistor (RCAT) | - |
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