Spatial Distribution of Interface Traps in Sub-50-nm Recess-Channel-Type DRAM Cell Transistors
- Authors
- Chung, Eun-Ae; Kim, Young-Pil; Park, Min-Chul; Nam, Kab-Jin; Lee, Sung-Sam; Min, Ji-Young; Yang, Giyoung; Shin, Yu-Gyun; Choi, Siyoung; Jin, Gyoyoung; Moon, Joo-Tae; Kim, Sangsig
- Issue Date
- 1월-2011
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Cell transistor; charge pumping (CP); interface traps; MOSFET; recessed-channel array transistor (RCAT)
- Citation
- IEEE ELECTRON DEVICE LETTERS, v.32, no.1, pp.81 - 83
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE ELECTRON DEVICE LETTERS
- Volume
- 32
- Number
- 1
- Start Page
- 81
- End Page
- 83
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/113356
- DOI
- 10.1109/LED.2010.2085416
- ISSN
- 0741-3106
- Abstract
- The spatial distribution of the interface traps in dynamic random access memory (DRAM) cell transistors having deeply recessed channels for sub-50-nm technology was evaluated by the charge pumping method and 3-D device simulations for the first time. The lateral distribution of the interface traps can be profiled before and after applying Fowler-Nordheim (F-N) gate stress. The experimental results show that the distribution of the interface traps is significantly correlated with the source/drain doping concentration, and this 3-D DRAM cell transistor was found to have greater immunity to F-N gate stress in the gate-drain overlapping region than in the channel region, due to the gate oxide thickness profile of the recess-channel-type structure. This lateral profiling of the interface traps in DRAM cell transistors should be very useful for refresh modeling and future DRAM device designs intended to improve the performance.
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