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카운터 기반 디지털 보상 기법을 이용한 위상 고정 루프Phase-Locked Loops using Digital Calibration Technique with counter
- Other Titles
- Phase-Locked Loops using Digital Calibration Technique with counter
- Authors
- 정찬희; Ammar Abdullah; 이관주; 김훈기; 김수원
- Issue Date
- 2011
- Publisher
- 대한전기학회
- Keywords
- Charge pump(CP) mismatch; Digital calibration; Charge pump phase-locked loop(CPPLL)
- Citation
- 전기학회논문지, v.60, no.2, pp.320 - 324
- Indexed
- SCOPUS
KCI
- Journal Title
- 전기학회논문지
- Volume
- 60
- Number
- 2
- Start Page
- 320
- End Page
- 324
- ISSN
- 1975-8359
- Abstract
- A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate 0.5μA current mismatch in CP. It was designed in a standard 0.13μm CMOS technology. The maximum calibration time is 33.6μs and the average power is 18.38mW with 1.5V power supply and effective area is 0.1804mm2.
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