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Compact Modeling for Circuit Simulation Considering TID Effect in 65nm CMOS TechnologyCompact Modeling for Circuit Simulation Considering TID Effect in 65nm CMOS Technology
- Alternative Title
- Compact Modeling for Circuit Simulation Considering TID Effect in 65nm CMOS Technology
- Authors
- Lee, Hyung-Min
- Issue Date
- 1-7월-2019
- Publisher
- IEIE & IEICE-ES
- Citation
- Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices
- Conference Name
- Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices
- Place
- KO
- Conference Date
- 2019-07-01
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Collections - College of Engineering > School of Electrical Engineering > 2. Conference Papers
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