Detailed Information

Cited 0 time in webofscience Cited 0 time in scopus
Metadata Downloads

Dynamic Parallel Computing Architecture for Video Processing

Authors
Bharanitharan, K.Paul, AnandJiang, Yung-ChuanWang, Jhing-Fa
Issue Date
Nov-2010
Publisher
LIBRARY & INFORMATION CENTER, NAT DONG HWA UNIV
Keywords
Motion estimation; Video coding; Parallel processing; Parallel architecture; FPGA
Citation
JOURNAL OF INTERNET TECHNOLOGY, v.11, no.6, pp.867 - 873
Indexed
SCIE
SCOPUS
Journal Title
JOURNAL OF INTERNET TECHNOLOGY
Volume
11
Number
6
Start Page
867
End Page
873
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/115358
ISSN
1607-9264
Abstract
In this paper, motion estimation preprocessing algorithm is mapped onto a new dynamically parallel computing architecture, namely, the parallel computing architecture, which consists of multiple parallel units It eventually reduces the computation required for motion estimation in advance video coding A directed acyclic graph is constructed to represent the video coding algorithms comprising motion estimation This speeds up the video processing with minimum sacrifice
Files in This Item
There are no files associated with this item.
Appears in
Collections
College of Engineering > School of Electrical Engineering > 1. Journal Articles

qrcode

Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.

Altmetrics

Total Views & Downloads

BROWSE