A New Class of Charge-Trap Flash Memory With Resistive Switching Mechanisms
DC Field | Value | Language |
---|---|---|
dc.contributor.author | An, Ho-Myoung | - |
dc.contributor.author | Lee, Eui Bok | - |
dc.contributor.author | Kim, Hee-Dong | - |
dc.contributor.author | Seo, Yu Jeong | - |
dc.contributor.author | Kim, Tae Geun | - |
dc.date.accessioned | 2021-09-07T23:56:32Z | - |
dc.date.available | 2021-09-07T23:56:32Z | - |
dc.date.created | 2021-06-14 | - |
dc.date.issued | 2010-10 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/115610 | - |
dc.description.abstract | This paper presents a new class of charge-trap Flash memory device with resistive switching mechanisms. We propose a fused memory scheme using a structure of metal/Pr-0.7 Ca-0.3 MnO3 (PCMO)/nitride/oxide/silicon to graft fast-switching features of resistive random access memory onto high-density silicon/oxide/nitride/oxide/silicon memory structures. In this scheme, both program and erase (P/E) are performed by the conduction of the carriers that are injected from the gate into the nitride layer through the PCMO, which is a resistive switching material; the resistance state determines whether a program or erase function is performed. In the proposed memory devices, we observed improved memory characteristics, including the current-voltage hysteresis having a resistive ratio exceeding three orders of magnitude at a set voltage of +/- 4.5 V, a memory window of 2.3 V, a P/E speed of 100 ns/1 ms, data retention of ten years, and endurance of 10(5) P/E cycles. This approach will offer critical clues about how one can best implement universal features of nonvolatile memories in a single chip. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | NONVOLATILE | - |
dc.subject | NANOCRYSTALS | - |
dc.subject | RESISTANCE | - |
dc.subject | STORAGE | - |
dc.subject | DEVICE | - |
dc.subject | NROM | - |
dc.subject | CELL | - |
dc.title | A New Class of Charge-Trap Flash Memory With Resistive Switching Mechanisms | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Tae Geun | - |
dc.identifier.doi | 10.1109/TED.2010.2063706 | - |
dc.identifier.scopusid | 2-s2.0-77957005281 | - |
dc.identifier.wosid | 000283346500004 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.57, no.10, pp.2398 - 2404 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.title | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.volume | 57 | - |
dc.citation.number | 10 | - |
dc.citation.startPage | 2398 | - |
dc.citation.endPage | 2404 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | NONVOLATILE | - |
dc.subject.keywordPlus | NANOCRYSTALS | - |
dc.subject.keywordPlus | RESISTANCE | - |
dc.subject.keywordPlus | STORAGE | - |
dc.subject.keywordPlus | DEVICE | - |
dc.subject.keywordPlus | NROM | - |
dc.subject.keywordPlus | CELL | - |
dc.subject.keywordAuthor | Charge-trap Flash (CTF) | - |
dc.subject.keywordAuthor | resistive random access memory (ReRAM) | - |
dc.subject.keywordAuthor | resistive switching | - |
dc.subject.keywordAuthor | silicon/oxide/nitride/oxide/silicon (SONOS) | - |
dc.subject.keywordAuthor | universal memory | - |
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