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Synthesis of Small Diameter Silicon Nanowires on SiO2 and Si3N4 Surfaces

Authors
Ahn, Jae HyunLee, Jae-HyunKoo, Tae-WoongKang, MyungGilWhang, DongmokHwang, SungWoo
Issue Date
5월-2010
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Keywords
silicon nanowire; VLS; bottom-up synthesis; selective growth
Citation
IEICE TRANSACTIONS ON ELECTRONICS, v.E93C, no.5, pp.546 - 551
Indexed
SCIE
SCOPUS
Journal Title
IEICE TRANSACTIONS ON ELECTRONICS
Volume
E93C
Number
5
Start Page
546
End Page
551
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/116498
DOI
10.1587/transele.E93.C.546
ISSN
0916-8524
Abstract
We report successful bottom-up synthesis of small diameter silicon nanowires (SiNWs) on SiO2 and Si3N4 surfaces. SiNWs with diameter comparable to the diameter of the Au nano-particles (10-20 nm) were grown on these surfaces, as well as on Si substrates which are commonly used for the nanowire growth. The growth temperature for obtaining a high density of SiNWs on SiO2 and Si3N4 substrates is higher (460-470 degrees C) than that of the case of normal Si substrates (440 degrees C). The growth on patterned substrates demonstrates that SiNWs can be selectively grown. Furthermore, the guided growth over metal structures is also shown to be possible. Selective growth of SiNWs on pre-patterned surfaces opens up the possibility of self-aligning SiNWs for the integration of complex device structures.
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