Suppression of Edge Effects Based on Analytic Model for Leakage Current Reduction of Sub-40 nm DRAM Device
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Soo Han | - |
dc.contributor.author | Park, Young Hee | - |
dc.contributor.author | Park, Chul Hong | - |
dc.contributor.author | Lee, Sang Hoon | - |
dc.contributor.author | Yoo, Moon Hyun | - |
dc.contributor.author | Cho, Jun Dong | - |
dc.contributor.author | Kim, Gyu Tae | - |
dc.date.accessioned | 2021-09-08T03:31:37Z | - |
dc.date.available | 2021-09-08T03:31:37Z | - |
dc.date.created | 2021-06-11 | - |
dc.date.issued | 2010-05 | - |
dc.identifier.issn | 0916-8524 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/116540 | - |
dc.description.abstract | With the process scaling, the leakage current reduction has been the primary design concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography process-aware edge effects correction method to reduce the leakage current in the shallow trench isolation (STI). We construct the various test structures to model I-leakage and I-leakage_fringe which represent the leakage currents at the center and edge of the transistor, respectively. The layout near the active edge is modified using the look-up table generated by the calibrated analytic model. On average, the proposed edge effects correction method reduces the leakage current by 18% with the negligible decrease of the drive current at sub-40nm DRAM device. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.title | Suppression of Edge Effects Based on Analytic Model for Leakage Current Reduction of Sub-40 nm DRAM Device | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Gyu Tae | - |
dc.identifier.doi | 10.1587/transele.E93.C.658 | - |
dc.identifier.scopusid | 2-s2.0-77951841959 | - |
dc.identifier.wosid | 000281341500025 | - |
dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON ELECTRONICS, v.E93C, no.5, pp.658 - 661 | - |
dc.relation.isPartOf | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.citation.title | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.citation.volume | E93C | - |
dc.citation.number | 5 | - |
dc.citation.startPage | 658 | - |
dc.citation.endPage | 661 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | edge effects | - |
dc.subject.keywordAuthor | analytic model | - |
dc.subject.keywordAuthor | retargeting | - |
dc.subject.keywordAuthor | shaping gate channels | - |
dc.subject.keywordAuthor | OPC | - |
dc.subject.keywordAuthor | leakage current | - |
dc.subject.keywordAuthor | drive current | - |
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