Suppression of Edge Effects Based on Analytic Model for Leakage Current Reduction of Sub-40 nm DRAM Device
- Authors
- Choi, Soo Han; Park, Young Hee; Park, Chul Hong; Lee, Sang Hoon; Yoo, Moon Hyun; Cho, Jun Dong; Kim, Gyu Tae
- Issue Date
- 5월-2010
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- edge effects; analytic model; retargeting; shaping gate channels; OPC; leakage current; drive current
- Citation
- IEICE TRANSACTIONS ON ELECTRONICS, v.E93C, no.5, pp.658 - 661
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEICE TRANSACTIONS ON ELECTRONICS
- Volume
- E93C
- Number
- 5
- Start Page
- 658
- End Page
- 661
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/116540
- DOI
- 10.1587/transele.E93.C.658
- ISSN
- 0916-8524
- Abstract
- With the process scaling, the leakage current reduction has been the primary design concerns in a nanometer-era VLSI circuit. In this paper, we propose a new lithography process-aware edge effects correction method to reduce the leakage current in the shallow trench isolation (STI). We construct the various test structures to model I-leakage and I-leakage_fringe which represent the leakage currents at the center and edge of the transistor, respectively. The layout near the active edge is modified using the look-up table generated by the calibrated analytic model. On average, the proposed edge effects correction method reduces the leakage current by 18% with the negligible decrease of the drive current at sub-40nm DRAM device.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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