A Novel Architecture for Block Interleaving Algorithm in MB-OFDM Using Mixed Radix System
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Han, Youngsun | - |
dc.contributor.author | Harliman, Peter | - |
dc.contributor.author | Kim, Seon Wook | - |
dc.contributor.author | Kim, Jong-Kook | - |
dc.contributor.author | Kim, Chulwoo | - |
dc.date.accessioned | 2021-09-08T09:56:13Z | - |
dc.date.available | 2021-09-08T09:56:13Z | - |
dc.date.created | 2021-06-11 | - |
dc.date.issued | 2010 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/118531 | - |
dc.description.abstract | In this paper, we present a novel architecture of a block interleaver inMB-OFDM systems based on Mixed Radix System (MRS). We prove mathematically that the proposed architecture can support bit permutations in the interleaving process. The hierarchical property of our proposed MRS-based design methodology allows the proposed architecture to support all the required data rates in the MB-OFDM systems with simple modular design. Furthermore, the same design to be used for the interleaver can also be used for the operation of de-interleaving, which reduces the implementation complexity significantly. The latency of our architecture is as low as 6 MB-OFDM symbols. In addition, when comparing our proposed architecture with the conventional approach, we are able to reduce the implementation complexity by 85.5%, 69.4%, and 40.3% for 80, 200, and 480 Mb/s data rates, respectively, while improving our operating maximum clock frequency by more than 3.3 times over the conventional design. We also show that the power consumption is reduced by 87.4%, 73.6%, and 39.8% for 80, 200, and 480 Mb/s, respectively. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | CONVERSION ALGORITHM | - |
dc.subject | CHANNEL | - |
dc.subject | CODES | - |
dc.title | A Novel Architecture for Block Interleaving Algorithm in MB-OFDM Using Mixed Radix System | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Seon Wook | - |
dc.contributor.affiliatedAuthor | Kim, Jong-Kook | - |
dc.contributor.affiliatedAuthor | Kim, Chulwoo | - |
dc.identifier.doi | 10.1109/TVLSI.2009.2018091 | - |
dc.identifier.scopusid | 2-s2.0-77952956319 | - |
dc.identifier.wosid | 000278435900019 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.18, no.6, pp.1020 - 1024 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 18 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 1020 | - |
dc.citation.endPage | 1024 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | CONVERSION ALGORITHM | - |
dc.subject.keywordPlus | CHANNEL | - |
dc.subject.keywordPlus | CODES | - |
dc.subject.keywordAuthor | Array processor | - |
dc.subject.keywordAuthor | block interleaving | - |
dc.subject.keywordAuthor | MB-OFDM | - |
dc.subject.keywordAuthor | Mixed Radix System (MRS) | - |
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