A Novel Architecture for Block Interleaving Algorithm in MB-OFDM Using Mixed Radix System
- Authors
- Han, Youngsun; Harliman, Peter; Kim, Seon Wook; Kim, Jong-Kook; Kim, Chulwoo
- Issue Date
- 2010
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Array processor; block interleaving; MB-OFDM; Mixed Radix System (MRS)
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.18, no.6, pp.1020 - 1024
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
- Volume
- 18
- Number
- 6
- Start Page
- 1020
- End Page
- 1024
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/118531
- DOI
- 10.1109/TVLSI.2009.2018091
- ISSN
- 1063-8210
- Abstract
- In this paper, we present a novel architecture of a block interleaver inMB-OFDM systems based on Mixed Radix System (MRS). We prove mathematically that the proposed architecture can support bit permutations in the interleaving process. The hierarchical property of our proposed MRS-based design methodology allows the proposed architecture to support all the required data rates in the MB-OFDM systems with simple modular design. Furthermore, the same design to be used for the interleaver can also be used for the operation of de-interleaving, which reduces the implementation complexity significantly. The latency of our architecture is as low as 6 MB-OFDM symbols. In addition, when comparing our proposed architecture with the conventional approach, we are able to reduce the implementation complexity by 85.5%, 69.4%, and 40.3% for 80, 200, and 480 Mb/s data rates, respectively, while improving our operating maximum clock frequency by more than 3.3 times over the conventional design. We also show that the power consumption is reduced by 87.4%, 73.6%, and 39.8% for 80, 200, and 480 Mb/s, respectively.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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