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Electrical Characteristics of Hybrid Nanoparticle-Nanowire Devices

Authors
Jeong, Dong-YoungKeem, KihyunPark, ByoungjunCho, KyoungahKim, Sangsig
Issue Date
Sep-2009
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
FET logic devices; FET memory integrated circuits; memories; nanotechnology
Citation
IEEE TRANSACTIONS ON NANOTECHNOLOGY, v.8, no.5, pp.650 - 653
Indexed
SCIE
SCOPUS
Journal Title
IEEE TRANSACTIONS ON NANOTECHNOLOGY
Volume
8
Number
5
Start Page
650
End Page
653
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/119379
DOI
10.1109/TNANO.2009.2021995
ISSN
1536-125X
Abstract
Gold nanoparticles synthesized by a colloidal method were deposited in an Al(2)O(3) dielectric layer of an omega-gated single ZnO nanowire FET. These gold nanoparticles were utilized as localized trap sites. The adsorption of the gold nanoparticles on an Al(2)O(3)-coated ZnO nanowire was confirmed by high-resolution transmission electron microscopy. In this study, a hybrid nanoparticle-nanowire device was fabricated by conventional Si processing. Its electrical characteristics indicated that electrons in the conduction band of the ZnO nanowire can be transported to the localized trap sites by gold nanoparticles for gate voltages greater than 1 V, through the 10-nm-thick Al(2)O(3) tunneling oxide layer.
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