A Simplified Superior Floating-Body/Gate DRAM Cell

Abstract

The basic concept of a simplified and easily manufacturable version of the two-transistor floating-body/gate DRAM cell (FBGC) is proposed and demonstrated via simulation and fabrication/experiment. Converting the charge-storage transistor (T1) to a gated diode enables easy and direct connection of its body to the gate of the sensing transistor in conventional planar SOI CMOS and in FinFET technologies, and also reduces the cell size. Numerical simulations show that the new cell can yield a much better signal margin and dissipate much less power than the one-transistor floating-body DRAM cells currently being assessed. A FinFET-based prototype of the new cell provides experimental corroboration of these features.