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VERIFICATION OF PLC PROGRAMS WRITTEN IN FBD WITH VIS
- Authors
- Yoo, Junbeom; Cha, Sungdeok; Jee, Eunkyoung
- Issue Date
- 2월-2009
- Publisher
- KOREAN NUCLEAR SOC
- Keywords
- Verification; Equivalence Checking; VIS; Verilog; Function Block Diagram; Programmable Logic Controller; IEC-61131
- Citation
- NUCLEAR ENGINEERING AND TECHNOLOGY, v.41, no.1, pp.79 - 90
- Indexed
- SCIE
SCOPUS
KCI
- Journal Title
- NUCLEAR ENGINEERING AND TECHNOLOGY
- Volume
- 41
- Number
- 1
- Start Page
- 79
- End Page
- 90
- ISSN
- 1738-5733
- Abstract
- Verification of programmable logic controller (PLC) programs written in IEC 61131-3 function block diagram (FBD) is essential in the transition from the use of traditional relay-based analog systems to PLC-based digital systems. This paper describes effective use of the well-known verification tool VIS for automatic verification of behavioral equivalences between successive FBD revisions. We formally defined FBD semantics as a state-transition system, developed semantic-preserving translation rules from FBD to Verilog programs, implemented a software tool to support the process, and conducted a case study on a subset of FBDs for APR-1400 reactor protection system design.
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