Fabrication and Characterization of Sidewall Defined Silicon-on-Insulator Single-Electron Transistor

Abstract

We reported the fabrication and characterization of a new type of silicon-on-insulator (SOI) single-electron transistor utilizing usual CMOS sidewall gate structures. We used oxide sidewall spacer layers as well as two poly-Si finger gates on an SOI wire mesa as implantation masks, to form tunnel barriers and thus a quantum dot (QD) that is smaller than the spacing between polygates. Characterization results exhibited clear Coulomb oscillations persisting up to 30 K. The Coulomb energy and the size of the QD extracted from three devices were consistent with the spacing between two poly-Si gates of each device. Furthermore, the junction capacitance of each device was almost constant and only the gate capacitance varied. These analyses suggested that the size of the QD was fully controlled by the process.