Exploiting thread-level parallelism in lockstep execution by partially duplicating a single pipeline
- Authors
- Oh, Jaegeun; Hwang, Seok Joong; Nguyen, Huong Giang; Kim, Areum; Kim, Seon Wook; Kim, Chulwoo; Kim, Jong-Kook
- Issue Date
- 8월-2008
- Publisher
- WILEY
- Keywords
- ILP; TLP; SMT; CMP; MLEP
- Citation
- ETRI JOURNAL, v.30, no.4, pp.576 - 586
- Indexed
- SCIE
SCOPUS
KCI
- Journal Title
- ETRI JOURNAL
- Volume
- 30
- Number
- 4
- Start Page
- 576
- End Page
- 586
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/122917
- DOI
- 10.4218/etrij.08.0107.0343
- ISSN
- 1225-6463
- Abstract
- in most parallel loops of embedded applications, every iteration executes the exact same sequence of instructions while manipulating different data. This fact motivates a new compiler-hardware orchestrated execution framework in which all parallel threads share one fetch unit and one decode unit but have their own execution, memory, and write-back units. This resource sharing enables parallel threads to execute in lockstep with minimal hardware extension and compiler support. Our proposed architecture, called multithreaded lockstep execution processor (MLEP), is a compromise between the single-instruction multiple-data (SIMD) and symmetric multithreading/chip multiprocessor (SMT/CMP) solutions. The proposed approach is more favorable than a typical SIMD execution in terms of degree of parallelism, range of applicability, and code generation, and can save more power and chip area than the SMT/CMP approach without significant performance degradation. For the architecture verification, we extend a commercial 32-bit embedded core AE32000C and synthesize it on Xilinx FPGA. Compared to the original architecture, our approach is 13.5% faster with a 2-way MLEP and 33.7% faster with a 4-way MLEP in EEMBC benchmarks which are automatically parallelized by the Intel compiler.
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Collections - College of Engineering > School of Electrical Engineering > 1. Journal Articles
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