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A pre-emphasis output buffer control scheme for a GDDR3 SDRAM interface
- Issue Date
- 25-6월-2008
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- GDDR3 SDRAM; termination; signal integrity
- Citation
- IEICE ELECTRONICS EXPRESS, v.5, no.12, pp.446 - 450
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEICE ELECTRONICS EXPRESS
- Volume
- 5
- Number
- 12
- Start Page
- 446
- End Page
- 450
- ISSN
- 1349-2543
- Abstract
- The keys to good signal integrity in a Graphic DDR3 (GDDR3) SDRAM interface for a bandwidth up to 1.4 Gbps/pin are the minimization of input/output pin capacitance and the accurate control of the output data skew. The proposed pre-emphasis output buffer control scheme provides output data skew minimization without an increase of input/output pin capacitance. Compared to the conventional scheme, the output data aperture window of proposed scheme has increased by 18% and the data output skew has decreased by 48%.
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