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On-demand solution to minimize I-cache leakage energy with maintaining performance

Authors
Chung, Sung WooSkadron, Kevin
Issue Date
1월-2008
Publisher
IEEE COMPUTER SOC
Keywords
microprocessor; instruction cache; leakage; branch predictor; wake-up policy
Citation
IEEE TRANSACTIONS ON COMPUTERS, v.57, no.1, pp.7 - 24
Indexed
SCIE
SCOPUS
Journal Title
IEEE TRANSACTIONS ON COMPUTERS
Volume
57
Number
1
Start Page
7
End Page
24
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/124480
DOI
10.1109/TC.2007.70770
ISSN
0018-9340
Abstract
This paper describes a new on-demand wake-up prediction policy for reducing leakage power. The key insight is that branch prediction can be used to selectively wake up only the needed cache line. This achieves better leakage savings than the best prior policies while avoiding the performance overheads of those policies, without needing an extra prediction structure. The proposed policy reduces leakage energy by 92.7 percent with only 0.08 percent performance overhead on average. The branch- prediction-based approach requires an extra pipeline stage for wake up, which adds to the branch misprediction penalty. Fortunately, this cost is mitigated because the extra wake-up stage is overlapped with misprediction recovery. This paper assumes the superdrowsy leakage control technique using reduced supply voltage because it is well suited to the instruction cache's criticality. However, the proposed policy can be also applied to other leakage- saving circuit techniques.
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