Enhancement of DRAM Performance by Adopting Metal-Interlayer-Semiconductor Source/Drain Contact Structure on DRAM Cell
DC Field | Value | Language |
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dc.contributor.author | Son, Muyeong | - |
dc.contributor.author | Jung, Seung Geun | - |
dc.contributor.author | Kim, Seung-Hwan | - |
dc.contributor.author | Park, Euyjin | - |
dc.contributor.author | Lee, Sul-Hwan | - |
dc.contributor.author | Yu, Hyun-Yong | - |
dc.date.accessioned | 2021-11-20T13:40:16Z | - |
dc.date.available | 2021-11-20T13:40:16Z | - |
dc.date.created | 2021-08-30 | - |
dc.date.issued | 2021-05 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/128118 | - |
dc.description.abstract | The effects of a metal-interlayersemiconductor (MIS) source/drain (S/D) contact structure on a dynamic random access memory (DRAM) cell transistor are investigated using 3-D technology computer-aided design simulation. WhentheMIS S/D contact structure is used in a DRAM cell, the retention time increases by approximately 16.22 times when compared with that of the device using the metal-semiconductor (MS) S/D contact structure owing to the lowered S/D doping concentration, leading to a decrement of the gate-induced drain leakage. Furthermore, the write time and charge-sharing time, respectively, are approximately 0.74 and 0.69 times shorter when compared with the device using the MS S/D contact structure owing to better ohmic characteristics, which increase the drain current during the write/read operations. Thus, the MIS S/D contact structure can effectively enhance the retention and write/read characteristics of a DRAM cell, and it can be a promising S/D contact alternative for the DRAM cell in the sub-2y-nm technology node. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | RESISTIVITY | - |
dc.subject | FUTURE | - |
dc.title | Enhancement of DRAM Performance by Adopting Metal-Interlayer-Semiconductor Source/Drain Contact Structure on DRAM Cell | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Yu, Hyun-Yong | - |
dc.identifier.doi | 10.1109/TED.2021.3066140 | - |
dc.identifier.scopusid | 2-s2.0-85103269930 | - |
dc.identifier.wosid | 000642766300019 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.68, no.5, pp.2275 - 2280 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.title | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.citation.volume | 68 | - |
dc.citation.number | 5 | - |
dc.citation.startPage | 2275 | - |
dc.citation.endPage | 2280 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | RESISTIVITY | - |
dc.subject.keywordPlus | FUTURE | - |
dc.subject.keywordAuthor | 3-D technology computer aided design (TCAD) simulation | - |
dc.subject.keywordAuthor | charge-sharing time | - |
dc.subject.keywordAuthor | contact resistance | - |
dc.subject.keywordAuthor | dynamic random access memory (DRAM) | - |
dc.subject.keywordAuthor | gate-induced drain leakage ( GIDL) | - |
dc.subject.keywordAuthor | metal-interlayer-semiconductor (MIS) | - |
dc.subject.keywordAuthor | retention time | - |
dc.subject.keywordAuthor | write time | - |
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