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Enhancement of DRAM Performance by Adopting Metal-Interlayer-Semiconductor Source/Drain Contact Structure on DRAM Cell

Authors
Son, MuyeongJung, Seung GeunKim, Seung-HwanPark, EuyjinLee, Sul-HwanYu, Hyun-Yong
Issue Date
5월-2021
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
3-D technology computer aided design (TCAD) simulation; charge-sharing time; contact resistance; dynamic random access memory (DRAM); gate-induced drain leakage ( GIDL); metal-interlayer-semiconductor (MIS); retention time; write time
Citation
IEEE TRANSACTIONS ON ELECTRON DEVICES, v.68, no.5, pp.2275 - 2280
Indexed
SCIE
SCOPUS
Journal Title
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume
68
Number
5
Start Page
2275
End Page
2280
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/128118
DOI
10.1109/TED.2021.3066140
ISSN
0018-9383
Abstract
The effects of a metal-interlayersemiconductor (MIS) source/drain (S/D) contact structure on a dynamic random access memory (DRAM) cell transistor are investigated using 3-D technology computer-aided design simulation. WhentheMIS S/D contact structure is used in a DRAM cell, the retention time increases by approximately 16.22 times when compared with that of the device using the metal-semiconductor (MS) S/D contact structure owing to the lowered S/D doping concentration, leading to a decrement of the gate-induced drain leakage. Furthermore, the write time and charge-sharing time, respectively, are approximately 0.74 and 0.69 times shorter when compared with the device using the MS S/D contact structure owing to better ohmic characteristics, which increase the drain current during the write/read operations. Thus, the MIS S/D contact structure can effectively enhance the retention and write/read characteristics of a DRAM cell, and it can be a promising S/D contact alternative for the DRAM cell in the sub-2y-nm technology node.
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공과대학 (전기전자공학부)
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