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A 360-fs-Time-Resolution 7-bit Stochastic Time-to-Digital Converter With Linearity Calibration Using Dual Time Offset Arbiters in 65-nm CMOS

Authors
Chung, HayunHyun, MinjiKim, Jungwon
Issue Date
Mar-2021
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Linearity; Calibration; Complexity theory; Systematics; Hardware; Switches; Signal resolution; Dual power supply; dual time offset arbiter; genetic algorithm (GA); linearity calibration; on-die variation; stochastic time-to-digital converter (STDC); ultra-fine time resolution
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.3, pp 940 - 949
Pages
10
Indexed
SCIE
SCOPUS
Journal Title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume
56
Number
3
Start Page
940
End Page
949
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/128469
DOI
10.1109/JSSC.2020.3036960
ISSN
0018-9200
1558-173X
Abstract
This article presents a 7-bit stochastic time-to-digital converter (STDC) with dual time offset arbiters that enables linearity calibration. The dual time offset arbiter with 1-bit mode selection effectively doubles time offsets available for time-to-digital conversion with minimal increase in hardware complexity. A genetic algorithm (GA)-based linearity calibration efficiently searches a huge search space to find the optimal time offset mode selection setting and a set of arbiters that lead to minimal integrated nonlinearity (INL). The combination of dual time offset arbiters and GA-based linearity calibration enables the proposed STDC to achieve ultrafine time resolution and a good linearity simultaneously. The proposed STDC also guarantees robust performance against on-die variation and gains good scalability with process technology as the linearity calibration is performed purely in the digital domain. A test chip prototype fabricated in a 65-nm CMOS technology demonstrates 360-fs time resolution with 0.75-LSB INL at 100 MS/s. The prototype achieves the effective time resolution of 630 fs, which is 1.5 times improvement compared with the prior arts.
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