Area and Energy Efficient Joint 2T SOT-MRAM-Based on Diffusion Region Sharing With Adjacent Cells
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jang, Yunho | - |
dc.contributor.author | Park, Jongsun | - |
dc.date.accessioned | 2022-04-12T10:42:04Z | - |
dc.date.available | 2022-04-12T10:42:04Z | - |
dc.date.created | 2022-04-12 | - |
dc.date.issued | 2022-03 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/140114 | - |
dc.description.abstract | In this brief, we present a novel low area joint 2T spin orbit torque magnetic random access memory (SOT-MRAM) cell architecture. The proposed joint 2T cell achieves up to 15 % of SOT-MRAM cell area reduction by sharing the diffusion regions of transistors between adjacent cells. In addition, the small bit-line capacitance of the proposed SOT-MRAM can lead to 27% read energy reduction in comparison to the conventional SOT-MRAM. When the proposed 1 MB SOT-MRAM is used as L2 cache of X86 processor, the gem5 simulation results show the average of 18% dynamic energy savings in various workloads of SPEC2006 benchmarks. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | TORQUE | - |
dc.subject | STT | - |
dc.title | Area and Energy Efficient Joint 2T SOT-MRAM-Based on Diffusion Region Sharing With Adjacent Cells | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Jongsun | - |
dc.identifier.doi | 10.1109/TCSII.2021.3126638 | - |
dc.identifier.scopusid | 2-s2.0-85127895902 | - |
dc.identifier.wosid | 000770045800195 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.69, no.3, pp.1622 - 1626 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.volume | 69 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 1622 | - |
dc.citation.endPage | 1626 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | TORQUE | - |
dc.subject.keywordPlus | STT | - |
dc.subject.keywordAuthor | Transistors | - |
dc.subject.keywordAuthor | Switches | - |
dc.subject.keywordAuthor | Computer architecture | - |
dc.subject.keywordAuthor | Layout | - |
dc.subject.keywordAuthor | Metals | - |
dc.subject.keywordAuthor | Capacitance | - |
dc.subject.keywordAuthor | Torque | - |
dc.subject.keywordAuthor | Spin orbit torque magnetic random access memory (SOT-MRAM) | - |
dc.subject.keywordAuthor | memory cell area | - |
dc.subject.keywordAuthor | memory cell structure | - |
dc.subject.keywordAuthor | memory operation energy | - |
dc.subject.keywordAuthor | cache | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
(02841) 서울특별시 성북구 안암로 14502-3290-1114
COPYRIGHT © 2021 Korea University. All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.