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Area and Energy Efficient Joint 2T SOT-MRAM-Based on Diffusion Region Sharing With Adjacent Cells

Authors
Jang, YunhoPark, Jongsun
Issue Date
3월-2022
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Keywords
Transistors; Switches; Computer architecture; Layout; Metals; Capacitance; Torque; Spin orbit torque magnetic random access memory (SOT-MRAM); memory cell area; memory cell structure; memory operation energy; cache
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.69, no.3, pp.1622 - 1626
Indexed
SCIE
SCOPUS
Journal Title
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume
69
Number
3
Start Page
1622
End Page
1626
URI
https://scholar.korea.ac.kr/handle/2021.sw.korea/140114
DOI
10.1109/TCSII.2021.3126638
ISSN
1549-7747
Abstract
In this brief, we present a novel low area joint 2T spin orbit torque magnetic random access memory (SOT-MRAM) cell architecture. The proposed joint 2T cell achieves up to 15 % of SOT-MRAM cell area reduction by sharing the diffusion regions of transistors between adjacent cells. In addition, the small bit-line capacitance of the proposed SOT-MRAM can lead to 27% read energy reduction in comparison to the conventional SOT-MRAM. When the proposed 1 MB SOT-MRAM is used as L2 cache of X86 processor, the gem5 simulation results show the average of 18% dynamic energy savings in various workloads of SPEC2006 benchmarks.
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Park, Jong sun
공과대학 (전기전자공학부)
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