Design of JL-CFET (junctionless complementary field effect transistor)-based inverter for low power applications
DC Field | Value | Language |
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dc.contributor.author | Lee, Sumi | - |
dc.contributor.author | Choi, Yejoo | - |
dc.contributor.author | Won, Sang Min | - |
dc.contributor.author | Son, Donghee | - |
dc.contributor.author | Baac, Hyoung Won | - |
dc.contributor.author | Shin, Changhwan | - |
dc.date.accessioned | 2022-05-11T07:29:30Z | - |
dc.date.available | 2022-05-11T07:29:30Z | - |
dc.date.created | 2022-03-14 | - |
dc.date.issued | 2022-03-01 | - |
dc.identifier.issn | 0268-1242 | - |
dc.identifier.uri | https://scholar.korea.ac.kr/handle/2021.sw.korea/140917 | - |
dc.description.abstract | Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (a) a high work function of metal gate and (b) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator's oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures. | - |
dc.language | English | - |
dc.language.iso | en | - |
dc.publisher | IOP Publishing Ltd | - |
dc.subject | NEGATIVE-CAPACITANCE | - |
dc.subject | FINFET | - |
dc.subject | PERFORMANCE | - |
dc.subject | CMOS | - |
dc.title | Design of JL-CFET (junctionless complementary field effect transistor)-based inverter for low power applications | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Shin, Changhwan | - |
dc.identifier.doi | 10.1088/1361-6641/ac41e6 | - |
dc.identifier.scopusid | 2-s2.0-85125454952 | - |
dc.identifier.wosid | 000749833800001 | - |
dc.identifier.bibliographicCitation | SEMICONDUCTOR SCIENCE AND TECHNOLOGY, v.37, no.3 | - |
dc.relation.isPartOf | SEMICONDUCTOR SCIENCE AND TECHNOLOGY | - |
dc.citation.title | SEMICONDUCTOR SCIENCE AND TECHNOLOGY | - |
dc.citation.volume | 37 | - |
dc.citation.number | 3 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Condensed Matter | - |
dc.subject.keywordPlus | NEGATIVE-CAPACITANCE | - |
dc.subject.keywordPlus | FINFET | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | CMOS | - |
dc.subject.keywordAuthor | CMOS inverter | - |
dc.subject.keywordAuthor | complementary FET (CFET) | - |
dc.subject.keywordAuthor | junctionless (JL) FET | - |
dc.subject.keywordAuthor | junctionless accumulation mode (JAM) FET | - |
dc.subject.keywordAuthor | metal ferroelectric insulator semiconductor (MFIS) | - |
dc.subject.keywordAuthor | negative capacitance (NC) | - |
dc.subject.keywordAuthor | self-heating effect (SHE) | - |
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