Design of JL-CFET (junctionless complementary field effect transistor)-based inverter for low power applications
- Authors
- Lee, Sumi; Choi, Yejoo; Won, Sang Min; Son, Donghee; Baac, Hyoung Won; Shin, Changhwan
- Issue Date
- 1-3월-2022
- Publisher
- IOP Publishing Ltd
- Keywords
- CMOS inverter; complementary FET (CFET); junctionless (JL) FET; junctionless accumulation mode (JAM) FET; metal ferroelectric insulator semiconductor (MFIS); negative capacitance (NC); self-heating effect (SHE)
- Citation
- SEMICONDUCTOR SCIENCE AND TECHNOLOGY, v.37, no.3
- Indexed
- SCIE
SCOPUS
- Journal Title
- SEMICONDUCTOR SCIENCE AND TECHNOLOGY
- Volume
- 37
- Number
- 3
- URI
- https://scholar.korea.ac.kr/handle/2021.sw.korea/140917
- DOI
- 10.1088/1361-6641/ac41e6
- ISSN
- 0268-1242
- Abstract
- Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (a) a high work function of metal gate and (b) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator's oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures.
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